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esmt m24d16161da elite semiconductor memory technology inc. publication date : jul. 2007 revision : 1.0 1/12 revision history : revision 1.0 (jul. 6, 2007) - original
esmt m24d16161da elite semiconductor memory technology inc. publication date : jul. 2007 revision : 1.0 2/12 psram 16-mbit (1m x 16) pseudo static ram features ? wide voltage range: 1.7v?1.95v ? access time: 70 ns ? ultra-low active power ? typical active current: 3 ma @ f = 1 mhz ? typical active current: 18 ma @ f = fmax ? ultra low standby power ? automatic power-down when deselected ? cmos for optimum speed/power ? available in 48-ball bga package ? operating temperatur e: ?40c to +85c functional description[1] the m24d16161da is a high-performance cmos pseudo static ram organized as 1m words by 16 bits that supports an asynchronous memory interf ace. this device features advanced circuit design to provide ultra-low active current. this is ideal portable applications such as cellular telephones. the device can be put into standby mode when deselected ( 1 ce high or ce2 low or both bhe and ble are high). the input/output pins (i/o 0 through i/o 15 ) are placed in a high-impedance state when : deselected ( 1 ce high or ce2 low), outputs are disabled ( oe high), both byte high enable and byte low enable are disabled ( bhe , ble high), or during a write operation ( 1 oe low and ce2 high and we low). to write to the device, take chip enable ( 1 ce low and ce2high) and write enable ( we ) input low. if byte low enable( ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a0through a 19 ). if byte high enable ( bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 19 ). to read from the device, take chip enables ( 1 ce low and ce2 high) and output enable ( oe ) low while forcing the write enable ( we ) high. if byte low enable ( ble ) is low, then data from the memory location specified by the address pins will appear on i/o0 to i/o7. if byte high enable ( bhe ) is low, then data from memory will appear on i/o 8 to i/o 15 .refer to the truth table for a complete description of read and write modes. logic block diagram
esmt m24d16161da elite semiconductor memory technology inc. publication date : jul. 2007 revision : 1.0 3/12 pin configuration[2, 3] 48-ball vfbga top view product portfolio[4] power dissipation operating i cc (ma) v cc range (v) speed(ns) f = 1mhz f = fmax standby i sb2 (a) product min. typ.[4] max .typ.[4] max . .typ.[4] max .typ. [4] max m24d16161da 1.7 1.8 1.95 70 3 5 18 20 55 70 power-up characteristics the initialization sequence is shown in the figure below. chip select should be 1 oe high or ce2 low for at least 200 s after v cc has reached a stable value. no access must be attempted during this period of 200 s. parameter description min. max. unit t pu chip enable low after stable v cc 200 s notes: 2.ball h6 and e3 can be used to upgrade to a 32-mbit and a 64-mbit density, respectively. 3.nc ?no connect?-not connect ed internally to the die. 4.typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc (typ) and t a = 25c. tested initially and after design chan ges that may affect the parameters.
esmt m24d16161da elite semiconductor memory technology inc. publication date : jul. 2007 revision : 1.0 4/12 maximum ratings (above which the useful life may be impaired. for user guide-lines, not tested.) storage temperature .............. ................ ...?65c to +150c ambient temperature with power applied........... .............. ................ ....?55c to +125c supply voltage to ground potential.?0.2v to v ccmax + 0.3v dc voltage applied to outputs in high z state[5, 6, 7]........................?0.2v to v ccmax + 0.3v dc input voltage[5, 6, 7 ]............... .....?0.2v to v ccmax + 0.3v output current into outputs (l ow).............................20 ma static discharge voltage......... ................ ............... .. > 2001v (per mil-std-883, method 3015) latch-up current............ ................. ............ ...........> 200 ma operating range range ambient temperature (t a ) v cc industrial ? 40c to +85c 1.7v to 1.95v dc electrical characteristics (over the operating range) [5, 6, 7] -70 parameter description test conditions min. typ.[4] max. unit v cc supply voltage 1.7 1.8 1.95 v v oh output high voltage i oh = ? 0.1 ma v cc = 1.7v to 1.95v v cc -0.2 v v ol output low voltage i ol = 0.1 ma, v cc = 1.7v to 1.95v 0.2 v v ih input high voltage v cc = 1.7v to 1.95v 0.8* v cc v cc +0.3v v v il input low voltage v cc = 1.7v to 1.95v -0.2 0.2* v cc v i ix input leakage current gnd v in v cc -1 +1 a i oz output leakage current gnd v out v cc -1 +1 a f = f max = 1/t rc v cc = v ccmax i out = 0ma cmos levels 18 25 ma i cc v cc operating supply current f = 1 mhz 3 5 ma i sb1 automatic ce power-down current ?cmos inputs ce v cc ? 0.2v, ce2 0.2v, v in > v cc ? 0.2v, v in < 0.2v, f = f max (address and data only), f = 0 ( oe , we , bhe and ble ), v cc =3.60v 55 70 a i sb2 automatic ce power-down current ?cmos inputs 1 ce v cc ? 0.2v, ce2 0.2v, v in v cc ? 0.2v or v in 0.2v, f = 0, v cc = v ccmax , 55 70 a capacitance[8] parameter description test conditions max. unit c in input capacitance 8 pf c out output capacitance t a = 25c, f = 1 mhz, v cc = v cc(typ) 8 pf thermal resistance[8] parameter description test conditions vfbga unit ? ja thermal resistance (junction to ambient) 56 c c/w ? jc thermal resistance (junction to case) test conditions follow standard test methods and procedures for measuring thermal impedence, per eia/jesd51. 11 c c/w notes: 5. v il(min) = ?0.5v for pulse durations less than 20 ns. 6.v ih(max) = v cc + 0.5v for pulse durations less than 20 ns. 7.overshoot and undershoot s pecifications are characteri zed and are not 100% tested. 8.tested initially and after any design or proce ss changes that may affect these parameters.
esmt m24d16161da elite semiconductor memory technology inc. publication date : jul. 2007 revision : 1.0 5/12 ac test loads and waveforms parameters 1.8v v cc unit r1 14000 ? r2 14000 ? r th 7000 ? v th 1.90 v switching characteristics over the operating range[9, 10, 11, 15, 14] -70 parameter description min. max. unit read cycle t rc [13] read cycle time 70 40000 ns t cd chip deselect time 1 ce =high or ce2=low, ble / bhe high pulse time 15 ns t aa address to data valid 70 ns t oha data hold from address change 5 ns t ace 1 ce low to data valid 70 ns t doe oe low to data valid 35 ns t lzoe oe low to low z[10, 11, 12] 5 ns t hzoe oe high to high z[10, 11, 12] 25 ns t lzce 1 ce low and ce2 high to low z[10, 11, 12] 10 ns t hzce 1 ce high and ce2 low to high z[10, 11, 12] 25 ns t dbe ble / bhe low to data valid 70 ns t lzbe ble / bhe low to low z[10, 11, 12] 5 ns t hzbe ble / bhe high to high z[10, 11, 12] 25 ns notes: 9. test conditions for all parameters other than tri-state parame ters assume signal transition time of 1 ns/v, timing reference levels of v cc(typ.) /2, input pulse levels of 0v to v cc , and output loading of the specified i ol /i oh as shown in the ?ac test loads and waveforms? section. 10. at any given temperature and voltage conditions t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. all low-z parameters will be measured with a load capacitance of 30 pf (3v). 11. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the out puts enter a high-impedance state. 12. high-z and low-z parameters are characterized and are not 100% tested. 13 .if invalid address sig nals shorter than min. t rc are continuously repeated for 40 s, the device needs a normal read timing (t rc ) or needs to enter standby state at least once in every 40 s. 14. in order to achieve 70-ns performance, the read access must be chip enable ( 1 ce or ce2) controlled. that is, the addresses must be stable prior to chip enable going active.
esmt m24d16161da elite semiconductor memory technology inc. publication date : jul. 2007 revision : 1.0 6/12 switching characteristics over the operating range[9, 10, 11, 15, 14] (continued) -70 parameter description min. max. unit write cycle[15] t wc write cycle time 70 40000 ns t sce 1 ce low and ce2 high to write end 60 ns t aw address set-up to write end 60 ns t cd chip deselect time 1 ce = high or ce2 = low, ble / bhe high pulse time 15 ns t ha address hold from write end 0 ns t sa address set-up to write start 0 ns t pwe we pulse width 50 ns t bw ble / bhe low to write end 60 ns t sd data set-up to write end 25 ns t hd data hold from write end 0 ns t hzwe we low to high-z[10, 11, 12] 25 ns t lzwe we high to low-z[10, 11, 12] 10 ns note: 15. the internal write time of the memory is defined by the overlap of we , 1 ce = v il or ce2 = v ih , bhe and/or ble = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input set-up and hold timing should be referenced to the edge of the signal t hat terminates the write.
esmt m24d16161da elite semiconductor memory technology inc. publication date : jul. 2007 revision : 1.0 7/12 switching wave forms read cycle 1 (address transition controlled)[17, 18] read cycle 2 ( oe controlled)[16, 18,19] notes: 16.whenever 1 ce = high or ce2 = low, bhe / ble are taken inactive, they must remain inactive for a minimum of 5 ns. 17.device is continuously selected. oe = 1 ce = v il and ce2 = v ih . 18. we is high for read cycle. 19. ce is the logical and of 1 ce and ce2.
esmt m24d16161da elite semiconductor memory technology inc. publication date : jul. 2007 revision : 1.0 8/12 switching waveforms (continued) notes: 20.data i/o is high-impedance if oe v ih . 21.during the don?t care period in the data i/o waveform, the i/os are in out put state and input signals should not be applied.
esmt m24d16161da elite semiconductor memory technology inc. publication date : jul. 2007 revision : 1.0 9/12 switching waveforms (continued) write cycle 2 ( 1 ce or ce2 controlled)[15, 12, 16, 20, 21] write cycle 3 ( we controlled, o e low)[16, 21]
esmt m24d16161da elite semiconductor memory technology inc. publication date : jul. 2007 revision : 1.0 10/12 switching waveforms (continued) write cycle 4 ( bhe / ble controlled, oe low)[15, 16, 20, 21] truth table[22] 1 ce ce2 we oe bhe ble inputs/outputs mode power h x x x x x high z deselect/power-down standby (i sb ) x l x x x x high z deselect/power-down standby (i sb ) x x x x h h high z deselect/power-down standby (i sb ) l h h l l l data out (i/o 0 ?i/o 15 ) read active (i cc ) l h h l h l data out (i/o 0 ?i/o 7 ); (i/o 8 ?i/o 15 ) in high z read active (i cc ) l h h l l h data out (i/o 8 ?i/o 15 ); (i/o 0 ?i/o 7 ) in high z read active (i cc ) l h h h l l high z output disabled active (i cc ) l h h h h l high z output disabled active (i cc ) l h h h l h high z output disabled active (i cc ) l h l x l l data in (i/o 0 ?i/o 15 ) write (upper byte and lower byte) active (i cc ) l h l x h l data in (i/o 0 ?i/o 7 ); (i/o 8 ?i/o 15 ) in high z write (lower byte only) active (i cc ) l h l x l h data out (i/o 8 ?i/o 15 ); (i/o 0 ?i/o 7 ) in high z write (upper byte only) active (i cc ) notes: 22.h = logic high, l = logic low, x = don?t care.
esmt m24d16161da elite semiconductor memory technology inc. publication date : jul. 2007 revision : 1.0 11/12 ordering information speed (ns) ordering code package type operating range 70 m24d16161da -70big 48-ball very fine pitch bga (6 x 8 x 1 mm) (pb-free) industrial package diagrams 48-ball vfbga (6 x 8 x 1 mm)
esmt m24d16161da elite semiconductor memory technology inc. publication date : jul. 2007 revision : 1.0 12/12 important notice all rights reserved. no part of this document may be rep roduced or duplicated in any form or by any means without the prior permission of esmt. the contents contained in this document are believed to be accurate at the time of publication. esmt assumes no responsibility for any error in this document, and reserves the right to change the produ cts or specification in this document without notice. the information contained h erein is presented only as a guide or examples for the application of our products. no res ponsibility is assumed by esmt for any infringement of patents, co pyrights, or other intellect ual property rights of third parties which may result from its use. no license, either express , implied or otherwise, is granted under any patent s, copyrights or other intellectual property rights of esmt or others. any semiconductor devices may have inher ently a certain rate of failure. to minimize risks associated with cust omer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer w hen making application designs. esmt's products are not authorized for use in critical applications such as, but not limited to, life support device s or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. if products described here are to be used for such kinds of application, purchaser must do its ow n quality assurance testing appropriate to such applications.

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